Exemplary embodiments relate generally to semiconductor devices and, more particularly to implantation of impurities in one or more conductive layers in fabricating a semiconductor device.
A polysilicon layer is often used for gate patterns in semiconductor devices. For example, a polysilicon layer may be used to form the floating gates in a NAND flash memory device having the structure advantageous for higher integration.
FIGS. 1A and 1B show the cross-sectional views of the conventional semiconductor devices including gate electrodes formed of a polysilicon layer, and more particularly related to forming floating gates in a NAND flash memory device.
Referring to FIG. 1A, an insulating layer 3, a first polysilicon layer 5, and a second polysilicon layer 7 are formed over a semiconductor substrate 1.
The insulating layer 3 is used to insulate the semiconductor substrate 1 from the gate electrodes, such as the floating gates to be formed over the semiconductor substrate 1. In particular, the insulating layer 3 is used as a tunnel insulating layer where the electrons from the floating gates above would pass through for storing or discharging the electrons of a NAND flash memory device.
The first polysilicon layer 5 and the second polysilicon layer 7 are conductive layers used as the gate electrodes such as the floating gates. There are more nano grain size crystals in the first polysilicon layer 5 adjoining the insulating layer 3 than in the second polysilicon layer 7. The first polysilicon layer 5 is formed of an undoped polysilicon layer without impurities. The second polysilicon layer 7 is formed of doped polysilicon having the impurities 9 in order to allow the gate electrodes (to be formed from the polysilicon layers 5 and 7) to have a low resistance value.
Referring to FIG. 1B, a hard mask pattern (not shown) is formed to cover certain predetermined portions of the second polysilicon layer 7 that are not to be etched, that is in subsequent processes. Using the hard mask pattern (not shown) as an etch mask, the first and second polysilicon layers 5 and 7 are etched, thereby forming polysilicon patterns P for floating gates. Further, again using the hard mask pattern as an etch mask, the insulating layer 3 and the predetermined portions of the semiconductor substrate 1 corresponding to the isolation regions may be etched by to form the trenches 11 in the isolation regions of the semiconductor substrate 1. Then, the trenches are filled with the isolation insulating layers 13 as shown in FIG. 1B such that active regions of the semiconductor substrate 1 are defined by the isolation insulating layers 13.
For high integration, the size of the polysilicon pattern P needs to be minimized. However, when the area of a polysilicon pattern P is sharply reduced, the poly depletion phenomenon will likely occur because of insufficient amount of impurities 9 being present in the polysilicon patterns P. Worsening poly depletion phenomenon will generate an error in the semiconductor device operations.
When the concentration of the impurities 9 in the second polysilicon layer 7 is increased as an attempt to minimize the poly depletion phenomenon, it may cause the impurities 9 in the second polysilicon layer 7 to be diffused by the heat generated in a subsequent process and cause the impurities 9 to accumulate near the insulating layer 3 that is used as the tunnel insulating layer. If the impurities 9 are accumulated near the insulating layer 3 used as the tunnel insulating layer, it will degrade the performance characteristics of the insulating layer 3 and cause the semiconductor device to malfunction.